The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon die. As the number of electronic devices per given area of a silicon wafer increases, manufacturing processes employed become more difficult.
An important subject of ongoing research in the semiconductor industry is a reduction in the dimensions of devices used in integrated circuits. Planar transistors such as metal oxide semiconductor (MOS) transistors are particularly suited to use in high density integrated circuits. As a size of MOS transistors and other active devices decreases, dimensions of the source/drain/gate electrodes, and the channel region of each device, must decrease commensurately.
When fabricating MOS transistors, source and drain electrodes are typically heavily doped to reduce a parasitic resistance of the device. While doping improves conductance, it concurrently increases parasitic capacitance, and lowers breakdown voltages. Many prior art devices interpose lightly doped drain (LDD) regions on either side of the channel region, between the channel region and the source/drain electrodes. LDD regions permit MOS devices to develop adequate breakdown voltages. However, LDD regions also increase the resistance between the source and drain when the transistor is turned on. This increased parasitic resistance degrades the switching speed and current carrying capabilities of the transistor. The necessity of LDD regions also adds process steps to fabrication which negatively affect both cost and reliability.
A MOS transistor suitable to control the gating and amplification of high speed signals must have a low parasitic capacitance, low parasitic resistance, and a breakdown voltage larger than the signals which are carried. These performance parameters represent design trade-offs well known to those skilled in the art of MOS transistor fabrication.
Most prior art MOS transistors have channel regions that are substantially the same size as the overlying gate electrode. The channel region size and shape is a direct result of implanting dopants in the silicon underlying the gate electrode to form source/drain electrodes and LDD regions, after the deposition of the gate electrode. The wide channel region formed in such a process contributes undesirable characteristics to a transistor's performance. It is commonly acknowledged that the drain current is inversely proportional to the length of the channel.
DMOS (double diffused metal oxide semiconductor) transistors are well known as a type of MOSFET (metal on semiconductor field effect transistor) using diffusions to form the transistor regions, with a typical application being as a power transistor. Such devices enjoy widespread use in such applications such as automobile electrical systems, power supplies, and power management applications.
In a DMOS transistor, a channel length is determined by the higher rate of diffusion of the P body region dopant (typically boron) compared to the N+ source region dopant (typically arsenic or phosphorus). The channel as defined by the body region overlies a lightly doped drift region. DMOS transistors can have very short channels and typically do not depend on photolithography to determine channel length. Such DMOS transistors have good punch-through control because of the heavily doped P body shield. The lightly doped drift region minimizes the voltage drop across the channel region by maintaining a uniform field to achieve a velocity saturation. The field near the drain region is the same as in the drift region so that avalanche breakdown, multiplication, and oxide charging are lessened as compared to conventional MOSFETs.
In one type of DMOS transistor, a trench is used to form a gate structure. These transistors are typically formed on <100> oriented silicon substrates (wafers), using an anisotropic etch to form the trench. When etched into <100> silicon, the trench has 54.7 degree sidewall slopes. The doping distribution is the same as the DMOS transistor described supra. The two channels are located one on each side of the etched trench. The device has a common drain contact at the bottom portion of the substrate. Since many devices can be connected in parallel, DMOS transistors can handle high current and high power so are suitable for power switching applications as described previously.
Many different processes have been used for the fabrication of power MOSFET devices over the years; these processes are generally deep diffusion processes. It is well known to form such transistors having a trench in the substrate, the trench being lined with a thin oxide layer and filled with a conductive polysilicon to form the transistor gate structure.
With reference to FIG. 1, a cross-sectional view of one prior art MOS device 100 includes a silicon substrate 101, an nwell 103, a threshold implant 105, a gate oxide 107, a liner oxide 109, a shallow-trench isolation (STI) oxide 111, a gate polysilicon region 113, and a resultant gate wrap-around region 115. The gate wrap-around region 115 is a result of contemporaneous MOS processing techniques causing a “divot” at a periphery of the STI oxide 111, as is well-known in the art. The gate wrap-around region 115, however, has at least the following detrimental affects to MOS device performance: (1) isolation voltages between gate and drift regions of a device are reduced; and (2) the divot produces a high capacitance region between the gate and drift regions, thereby creating a high local-electric field. Therefore, what is needed is an economical method to produce a MOS device while eliminating the deleterious effects of the gate wrap-around region by eliminating the divot during processing.